C8051F124-GQR Datasheet, PDF (307/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 22.4. Timer Settings for Standard Baud Rates Using the PLL
Frequency: 50.0 MHz
Target Baud Rate Oscilla- Timer Clock SCA1-SCA0 T1M* Timer 1
Baud Rate
(bps)
% Error tor Divide
Factor
Source
(pre-scale
select)*
Reload
Value (hex)
230400
0.45%
218
SYSCLK
XX
1
0x93
115200
-0.01%
434
SYSCLK
XX
1
0x27
57600
0.45%
872
SYSCLK / 4
01
0
0x93
28800
-0.01%
1736 SYSCLK / 4
01
0
0x27
14400
0.22%
3480 SYSCLK / 12
00
0
0x6F
9600
-0.01%
5208 SYSCLK / 12
00
0
0x27
2400
-0.01%
20832 SYSCLK / 48
10
0
0x27
X = Don’t care
*Note: SCA1-SCA0 and T1M bit definitions can be found in Section 23.1.
Table 22.5. Timer Settings for Standard Baud Rates Using the PLL
Frequency: 100.0 MHz
Target Baud Rate Oscilla- Timer Clock
Baud Rate % Error tor Divide Source
(bps)
Factor
SCA1-SCA0
(pre-scale
select)*
T1M* Timer 1
Reload
Value (hex)
230400
-0.01%
434
SYSCLK
XX
1
0x27
115200
0.45%
872
SYSCLK / 4
01
0
0x93
57600
-0.01%
1736 SYSCLK / 4
01
0
0x27
28800
0.22%
3480 SYSCLK / 12
00
0
0x6F
14400
-0.47%
6912 SYSCLK / 48
10
0
0xB8
9600
0.45%
10464 SYSCLK / 48
10
0
0x93
X = Don’t care
*Note: SCA1-SCA0 and T1M bit definitions can be found in Section 23.1.
Rev. 1.4
307