C8051F124-GQR Datasheet, PDF (341/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
25. JTAG (IEEE 1149.1)
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-sys-
tem testing, Flash read/write operations, and non-intrusive in-circuit debug. The JTAG interface is fully
compliant with the IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test
Interface and Boundary-Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Regis-
ters (DR) are as described in the Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is accessed via four dedicated pins on the MCU: TCK, TMS, TDI, and TDO.
Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 25.1 can
be commanded. There are three DR’s associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
JTAG Register Definition 25.1. IR: JTAG Instruction Register
Bit15
Reset Value
0x0000
Bit0
IR Value Instruction
Description
0x0000
EXTEST
Selects the Boundary Data Register for control and observability of all
device pins
0x0002
SAMPLE/ Selects the Boundary Data Register for observability and presetting the
PRELOAD scan-path latches
0x0004 IDCODE Selects device ID Register
0xFFFF BYPASS Selects Bypass Data Register
0x0082
Flash Control
Selects FLASHCON Register to control how the interface logic responds
to reads and writes to the FLASHDAT Register
0x0083 Flash Data Selects FLASHDAT Register for reads and writes to the Flash memory
0x0084
Flash Address
Selects FLASHADR Register which holds the address of all Flash read,
write, and erase operations
0x0085
Flash Scale
Selects FLASHSCL Register which controls the Flash one-shot timer and
read-always enable
Rev. 1.4
341