C8051F124-GQR Datasheet, PDF (251/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 18.10. P2MDOUT: Port2 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits7–0: P2MDOUT.[7:0]: Port2 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
R/W
R/W
Reset Value
00000000
Bit1
Bit0
SFR Address: 0xA6
SFR Page: F
Note:
SDA, SCL, and RX0 (when UART0 is in Mode 0) and RX1 (when UART1 is in Mode 0) are
always configured as Open-Drain when they appear on Port pins.
SFR Definition 18.11. P3: Port3 Data
R/W
P3.7
Bit7
R/W
P3.6
Bit6
R/W
P3.5
Bit5
R/W
P3.4
Bit4
R/W
P3.3
Bit3
R/W
P3.2
Bit2
R/W
P3.1
Bit1
R/W
Reset Value
P3.0 11111111
Bit0
Bit
Addressable
SFR Address: 0xB0
SFR Page: All Pages
Bits7–0:
P3.[7:0]: Port3 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P3MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P3.n pin is logic low.
1: P3.n pin is logic high.
Note:
P3.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed
mode, or as D[7:0] in Non-multiplexed mode). See Section “17. External Data Memory
Interface and On-Chip XRAM” on page 219 for more information about the External Memory
Interface.
Rev. 1.4
251