C8051F124-GQR Datasheet, PDF (164/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
11.4.2. Stop Mode
Setting the Stop Mode Select bit (PCON.1) causes the CIP-51 to enter Stop mode as soon as the instruc-
tion that sets the bit completes. In Stop mode, the CPU and oscillators are stopped, effectively shutting
down all digital peripherals. Each analog peripheral must be shut down individually prior to entering Stop
Mode. Stop mode can only be terminated by an internal or external reset. On reset, the CIP-51 performs
the normal reset sequence and begins program execution at address 0x00000.
If enabled, the Missing Clock Detector will cause an internal reset and thereby terminate the Stop mode.
The Missing Clock Detector should be disabled if the CPU is to be put to sleep for longer than the MCD
timeout of 100 µs.
SFR Definition 11.18. PCON: Power Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
-
-
-
-
-
-
STOP IDLE 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x87
SFR Page: All Pages
Bits7–3:
Bit1:
Bit0:
Reserved.
STOP: STOP Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into STOP mode. This bit will always read ‘0’.
1: CIP-51 forced into power-down mode. (Turns off oscillator).
IDLE: IDLE Mode Select.
Writing a ‘1’ to this bit will place the CIP-51 into IDLE mode. This bit will always read ‘0’.
1: CIP-51 forced into IDLE mode. (Shuts off clock to CPU, but clock to Timers, Interrupts,
and all peripherals remain active.)
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Rev. 1.4