C8051F124-GQR Datasheet, PDF (293/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
21.2. Multiprocessor Communications
Modes 2 and 3 support multiprocessor communication between a master processor and one or more slave
processors by special use of the ninth data bit and the built-in UART0 address recognition hardware. When
a master processor wants to transmit to one or more slaves, it first sends an address byte to select the tar-
get(s). An address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is
always set to logic 0. UART0 will recognize as “valid” (i.e., capable of causing an interrupt) two types of
addresses: (1) a masked address and (2) a broadcast address at any given time. Both are described
below.
21.2.1. Configuration of a Masked Address
The UART0 address is configured via two SFR’s: SADDR0 (Serial Address) and SADEN0 (Serial Address
Enable). SADEN0 sets the bit mask for the address held in SADDR0: bits set to logic 1 in SADEN0 corre-
spond to bits in SADDR0 that are checked against the received address byte; bits set to logic 0 in SADEN0
correspond to “don’t care” bits in SADDR0.
Example 1, SLAVE #1
SADDR0
= 00110101
SADEN0
= 00001111
UART0 Address = xxxx0101
Example 2, SLAVE #2
SADDR0
= 00110101
SADEN0
= 11110011
UART0 Address = 0011xx01
Example 3, SLAVE #3
SADDR0
= 00110101
SADEN0
= 11000000
UART0 Address = 00xxxxxx
Setting the SM20 bit (SCON0.5) configures UART0 such that when a stop bit is received, UART0 will gen-
erate an interrupt only if the ninth bit is logic 1 (RB80 = ‘1’) and the received data byte matches the UART0
slave address. Following the received address interrupt, the slave will clear its SM20 bit to enable interrupts
on the reception of the following data byte(s). Once the entire message is received, the addressed slave
resets its SM20 bit to ignore all transmissions until it receives the next address byte. While SM20 is logic 1,
UART0 ignores all bytes that do not match the UART0 address and include a ninth bit that is logic 1.
21.2.2. Broadcast Addressing
Multiple addresses can be assigned to a single slave and/or a single address can be assigned to multiple
slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. The broadcast
address is the logical OR of registers SADDR0 and SADEN0, and ‘0’s of the result are treated as “don’t
cares”. Typically a broadcast address of 0xFF (hexadecimal) is acknowledged by all slaves, assuming
“don’t care” bits as ‘1’s. The master processor can be configured to receive all transmissions or a protocol
can be implemented such that the master/slave role is temporarily reversed to enable half-duplex trans-
mission between the original master and slave(s)..
Example 4, SLAVE #1
Example 5, SLAVE #2
Example 6, SLAVE #3
SADDR0
= 00110101
SADDR0
= 00110101
SADDR0
= 00110101
SADEN0
= 00001111
SADEN0
= 11110011
SADEN0
= 11000000
Broadcast Address = 00111111 Broadcast Address = 11110111 Broadcast Address = 11110101
Where all ZEROES in the Broadcast address are don’t cares.
Note in the above examples 4, 5, and 6, each slave would recognize as “valid” an address of 0xFF as a
broadcast address. Also note that examples 4, 5, and 6 uses the same SADDR0 and SADEN0 register
values as shown in the examples 1, 2, and 3 respectively (slaves #1, 2, and 3). Thus, a master could
address each slave device individually using a masked address, and also broadcast to all three slave
devices. For example, if a Master were to send an address “11110101”, only slave #1 would recognize the
address as valid. If a master were to then send an address of “11111111”, all three slave devices would rec-
ognize the address as a valid broadcast address.
Rev. 1.4
293