C8051F124-GQR Datasheet, PDF (305/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 22.2. SBUF1: Serial (UART1) Port Data Buffer
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x99
SFR Page: 1
Bits7–0:
SBUF1[7:0]: Serial Data Buffer Bits 7-0 (MSB-LSB)
This SFR accesses two registers; a transmit shift register and a receive latch register. When
data is written to SBUF1, it goes to the transmit shift register and is held for serial transmis-
sion. Writing a byte to SBUF1 is what initiates the transmission. A read of SBUF1 returns the
contents of the receive latch.
Table 22.1. Timer Settings for Standard Baud Rates Using The Internal 24.5 MHz
Oscillator
Frequency: 24.5 MHz
Target Baud Rate Oscilla- Timer Clock SCA1-SCA0 T1M* Timer 1
Baud Rate % Error tor Divide Source
(pre-scale
Reload
(bps)
Factor
select)*
Value (hex)
230400
-0.32%
106
SYSCLK
XX
1
0xCB
115200
-0.32%
212
SYSCLK
XX
1
0x96
57600
0.15%
426
SYSCLK
XX
1
0x2B
28800
-0.32%
848 SYSCLK / 4
01
0
0x96
14400
0.15%
1704 SYSCLK / 12
00
0
0xB9
9600
-0.32%
2544 SYSCLK / 12
00
0
0x96
2400
-0.32%
10176 SYSCLK / 48
10
0
0x96
1200
0.15%
20448 SYSCLK / 48
10
0
0x2B
X = Don’t care
*Note: SCA1-SCA0 and T1M bit definitions can be found in Section 23.1.
Rev. 1.4
305