C8051F124-GQR Datasheet, PDF (254/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 18.13. P4: Port4 Data
R/W
P4.7
Bit7
R/W
P4.6
Bit6
R/W
P4.5
Bit5
R/W
P4.4
Bit4
R/W
P4.3
Bit3
R/W
P4.2
Bit2
R/W
P4.1
Bit1
R/W
Reset Value
P4.0 11111111
Bit0
Bit
Addressable
SFR Address: 0xC8
SFR Page: F
Bits7–0:
P4.[7:0]: Port4 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P4MDOUT.n bit = 0). See SFR Definition
18.14.
Read - Returns states of I/O pins.
0: P4.n pin is logic low.
1: P4.n pin is logic high.
Note:
P4.7 (/WR), P4.6 (/RD), and P4.5 (ALE) can be driven by the External Data Memory Interface.
See Section “17. External Data Memory Interface and On-Chip XRAM” on page 219 for
more information.
SFR Definition 18.14. P4MDOUT: Port4 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits7–0: P4MDOUT.[7:0]: Port4 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
R/W
R/W
Reset Value
00000000
Bit1
Bit0
SFR Address: 0x9C
SFR Page: F
254
Rev. 1.4