C8051F124-GQR Datasheet, PDF (166/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
12.2. Integer and Fractional Math
MAC0 is capable of interpreting the 16-bit inputs stored in MAC0A and MAC0B as signed integers or as
signed fractional numbers. When the MAC0FM bit (MAC0CF.1) is cleared to ‘0’, the inputs are treated as
16-bit, 2’s complement, integer values. After the operation, the accumulator will contain a 40-bit, 2’s com-
plement, integer value. Figure 12.2 shows how integers are stored in the SFRs.
MAC0A and MAC0B Bit Weighting
High Byte
Low Byte
-(2¹⁵) 2¹⁴ 2¹³ 2¹² 2¹¹ 2¹⁰ 2⁹
2⁸
2⁷
2⁶
2⁵
2⁴
2³
2²
2¹
2⁰
MAC0OVR
-(2³⁹) 2³⁸
2³³
MAC0 Accumulator Bit Weighting
MAC0ACC3 : MAC0ACC2 : MAC0ACC1 : MAC0ACC0
2³²
2³¹ 2³⁰ 2²⁹ 2²⁸
2⁴
2³
2²
2¹
2⁰
Figure 12.2. Integer Mode Data Representation
When the MAC0FM bit is set to ‘1’, the inputs are treated at 16-bit, 2’s complement, fractional values. The
decimal point is located between bits 15 and 14 of the data word. After the operation, the accumulator will
contain a 40-bit, 2’s complement, fractional value, with the decimal point located between bits 31 and 30.
Figure 12.3 shows how fractional numbers are stored in the SFRs.
MAC0A, and MAC0B Bit Weighting
High Byte
Low Byte
-1
2^-1
2^-2
2^-3 2^-4
2^-5
2^-6
2^-7
2^-8
2^-9 2^-10 2^-11 2^-12 2^-13 2^-14 2^-15
MAC0OVR
-(2⁸) 2⁷
2²
MAC0 Accumulator Bit Weighting
MAC0ACC3 : MAC0ACC2 : MAC0ACC1 : MAC0ACC0
2¹
2⁰
2^-1
2^-2
2^-3
2^-27 2^-28 2^-29 2^-30 2^-31
MAC0RND Bit Weighting
High Byte
Low Byte
* -2
1
2^-1 2^-2 2^-3 2^-4 2^-5 2^-6 2^-7
2^-8 2^-9 2^-10 2^-11 2^-12 2^-13 2^-14 2^-15
* The MAC0RND register contains the 16 LSBs of a two's complement number. The MAC0N Flag can be
used to determine the sign of the MAC0RND register.
Figure 12.3. Fractional Mode Data Representation
166
Rev. 1.4