C8051F124-GQR Datasheet, PDF (287/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
21. UART0
UART0 is an enhanced serial port with frame error detection and address recognition hardware. UART0
may operate in full-duplex asynchronous or half-duplex synchronous modes, and mutiproccessor commu-
nication is fully supported. Receive data is buffered in a holding register, allowing UART0 to start reception
of a second incoming data byte before software has finished reading the previous data byte. A Receive
Overrun bit indicates when new received data is latched into the receive buffer before the previously
received byte has been read.
UART0 is accessed via its associated SFR’s, Serial Control (SCON0) and Serial Data Buffer (SBUF0). The
single SBUF0 location provides access to both transmit and receive registers. Reading SCON0 accesses
the Receive register and writing SCON0 accesses the Transmit register.
UART0 may be operated in polled or interrupt mode. UART0 has two sources of interrupts: a Transmit
Interrupt flag, TI0 (SCON0.1) set when transmission of a data byte is complete, and a Receive Interrupt
flag, RI0 (SCON0.0) set when reception of a data byte is complete. UART0 interrupt flags are not cleared
by hardware when the CPU vectors to the interrupt service routine; they must be cleared manually by soft-
ware. This allows software to determine the cause of the UART0 interrupt (transmit complete or receive
complete).
SFR Bus
Write to
SBUF0
TB80
SSTA0
FRTSSSSS
EXXM0 0 0 0
0 OCOT TRR
VODCCCC
0L0LLLL
0 KKKK
1111
UART0
Baud Rate Generation
Logic
SET
DQ
CLR
SBUF0
Zero Detector
Stop Bit
Gen.
Start
Tx Clock
Shift
Tx Control
Tx IRQ
Data
Send
SCON0
TI0
SSSRTRTR
MMME B B I I
0 1 2N8 8 0 0
000000
RI0
Rx Clock
Start
EN
Rx IRQ
Rx Control
Shift
0x1FF
Load
SBUF
Address
Match
TX0
Crossbar
Serial Port
(UART0) Interrupt
Port I/O
Frame Error
Detection
Input Shift Register
(9 bits)
Load
SBUF0
RB80
SBUF0
Match Detect
Read
SBUF0
SADDR0
SADEN0
SFR Bus
RX0
Crossbar
Figure 21.1. UART0 Block Diagram
Rev. 1.4
287