C8051F124-GQR Datasheet, PDF (158/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 11.13. IP: Interrupt Priority
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
-
-
PT2
PS0
PT1
PX1
PT0
PX0 11000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0xB8
SFR Page: All Pages
Bits7–6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
UNUSED. Read = 11b, Write = don't care.
PT2: Timer 2 Interrupt Priority Control.
This bit sets the priority of the Timer 2 interrupt.
0: Timer 2 interrupt set to low priority.
1: Timer 2 interrupt set to high priority.
PS0: UART0 Interrupt Priority Control.
This bit sets the priority of the UART0 interrupt.
0: UART0 interrupt set to low priority.
1: UART0 interrupts set to high priority.
PT1: Timer 1 Interrupt Priority Control.
This bit sets the priority of the Timer 1 interrupt.
0: Timer 1 interrupt set to low priority.
1: Timer 1 interrupts set to high priority.
PX1: External Interrupt 1 Priority Control.
This bit sets the priority of the External Interrupt 1 interrupt.
0: External Interrupt 1 set to low priority.
1: External Interrupt 1 set to high priority.
PT0: Timer 0 Interrupt Priority Control.
This bit sets the priority of the Timer 0 interrupt.
0: Timer 0 interrupt set to low priority.
1: Timer 0 interrupt set to high priority.
PX0: External Interrupt 0 Priority Control.
This bit sets the priority of the External Interrupt 0 interrupt.
0: External Interrupt 0 set to low priority.
1: External Interrupt 0 set to high priority.
158
Rev. 1.4