C8051F124-GQR Datasheet, PDF (345/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
JTAG Register Definition 25.3. FLASHCON: JTAG Flash Control
SFLE
Bit7
WRMD2 WRMD1 WRMD0
Bit6
Bit5
Bit4
RDMD3
Bit3
RDMD2
Bit2
RDMD1
Bit1
RDMD0
Bit0
Reset Value
00000000
This register determines how the Flash interface logic will respond to reads and writes to the FLASH-
DAT Register.
Bit7:
Bits6–4:
Bits3–0:
SFLE: Scratchpad Flash Memory Access Enable
When this bit is set, Flash reads and writes are directed to the two 128-byte Scratchpad
Flash sectors. When SFLE is set to logic 1, Flash accesses out of the address range 0x00-
0xFF should not be attempted (with the exception of address 0x400, which can be used to
simultaneously erase both Scratchpad areas). Reads/Writes out of this range will yield
undefined results.
0: Flash access directed to the Program/Data Flash sector.
1: Flash access directed to the two 128 byte Scratchpad sectors.
WRMD2–0: Write Mode Select Bits.
The Write Mode Select Bits control how the interface logic responds to writes to the FLASH-
DAT Register per the following values:
000: A FLASHDAT write replaces the data in the FLASHDAT register, but is otherwise
ignored.
001: A FLASHDAT write initiates a write of FLASHDAT into the memory address by the
FLASHADR register. FLASHADR is incremented by one when complete.
010: A FLASHDAT write initiates an erasure (sets all bytes to 0xFF) of the Flash page
containing the address in FLASHADR. The data written must be 0xA5 for the erase
to occur. FLASHADR is not affected. If FLASHADR = 0x1FBFE – 0x1FBFF, the
entire user space will be erased (i.e. entire Flash memory except for Reserved area
0x1FC00 – 0x1FFFF).
(All other values for WRMD2-0 are reserved.)
RDMD3–0: Read Mode Select Bits.
The Read Mode Select Bits control how the interface logic responds to reads from the
FLASHDAT Register per the following values:
0000: A FLASHDAT read provides the data in the FLASHDAT register, but is otherwise
ignored.
0001: A FLASHDAT read initiates a read of the byte addressed by the FLASHADR register
if no operation is currently active. This mode is used for block reads.
0010: A FLASHDAT read initiates a read of the byte addressed by FLASHADR only if no
operation is active and any data from a previous read has already been read from
FLASHDAT. This mode allows single bytes to be read (or the last byte of a block)
without initiating an extra read.
(All other values for RDMD3–0 are reserved.)
Rev. 1.4
345