C8051F124-GQR Datasheet, PDF (32/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
1.5. Programmable Digital I/O and Crossbar
The standard 8051 8-bit Ports (0, 1, 2, and 3) are available on the MCUs. The devices in the larger (100-
pin TQFP) packaging have 4 additional ports (4, 5, 6, and 7) for a total of 64 general-purpose port I/O. The
Port I/O behave like the standard 8051 with a few enhancements.
Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the "weak pullups"
which are normally fixed on an 8051 can be globally disabled, providing additional power saving capabili-
ties for low-power applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is a large digital switching network that
allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3. (See
Figure 1.11) Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are
supported.
The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion inputs, comparator out-
puts, and other digital signals in the controller can be configured to appear on the Port I/O pins specified in
the Crossbar Control registers. This allows the user to select the exact mix of general purpose Port I/O and
digital resources needed for the particular application.
Highest
Priority
Lowest
Priority
Port
Latches
UART0
2
4
SPI
2
SMBus
2
UART1
7
PCA
XBR0, XBR1,
XBR2, P1MDIN
Registers
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
Priority
Decoder
8
P0
I/O
Cells
Comptr.
2
Outputs
T0, T1,
T2, T2EX,
8
T4,T4EX
/INT0,
/INT1
/SYSCLK divided by 1,2,4, or 8
CNVSTR0/2
2
8
P0 _(P0.0-P0.7)
8
P1 _(P1.0-P1.7)
8
P2 _(P2.0-P2.7)
8
P3 _(P3.0-P3.7)
Digital
Crossbar
8
8
8
P1
I/O
Cells
P2
I/O
Cells
P3
I/O
Cells
To External
Memory
Interface
(EMIF)
To ADC2 Input
(‘F12x Only)
Figure 1.11. Digital Crossbar Diagram
External
Pins
P0.0
P0.7
Highest
Priority
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Lowest
Priority
32
Rev. 1.4