C8051F124-GQR Datasheet, PDF (306/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 22.2. Timer Settings for Standard Baud Rates Using an External 25.0 MHz
Oscillator
Frequency: 25.0 MHz
Target Baud Rate Oscilla- Timer Clock SCA1-SCA0 T1M* Timer 1
Baud Rate % Error tor Divide Source
(pre-scale
Reload
(bps)
Factor
select)*
Value (hex)
230400
-0.47%
108
SYSCLK
XX
1
0xCA
115200
0.45%
218
SYSCLK
XX
1
0x93
57600
-0.01%
434
SYSCLK
XX
1
0x27
28800
0.45%
872 SYSCLK / 4
01
0
0x93
14400
-0.01%
1736 SYSCLK / 4
01
0
0x27
9600
0.15%
2608 EXTCLK / 8
11
0
0x5D
2400
0.45%
10464 SYSCLK / 48
10
0
0x93
1200
-0.01%
20832 SYSCLK / 48
10
0
0x27
57600
-0.47%
432
EXTCLK / 8
11
0
0xE5
28800
-0.47%
864
EXTCLK / 8
11
0
0xCA
14400
0.45%
1744 EXTCLK / 8
11
0
0x93
9600
0.15%
2608 EXTCLK / 8
11
0
0x5D
X = Don’t care
*Note: SCA1-SCA0 and T1M bit definitions can be found in Section 23.1.
Table 22.3. Timer Settings for Standard Baud Rates Using an External 22.1184 MHz
Oscillator
Frequency: 22.1184 MHz
Target Baud Rate Oscilla- Timer Clock
Baud Rate % Error tor Divide Source
(bps)
Factor
SCA1-SCA0
(pre-scale
select)*
T1M* Timer 1
Reload
Value (hex)
230400
0.00%
96
SYSCLK
XX
1
0xD0
115200
0.00%
192
SYSCLK
XX
1
0xA0
57600
0.00%
384
SYSCLK
XX
1
0x40
28800
0.00%
768 SYSCLK / 12
00
0
0xE0
14400
0.00%
1536 SYSCLK / 12
00
0
0xC0
9600
0.00%
2304 SYSCLK / 12
00
0
0xA0
2400
0.00%
9216 SYSCLK / 48
10
0
0xA0
1200
0.00%
18432 SYSCLK / 48
10
0
0x40
230400
0.00%
96
EXTCLK / 8
11
0
0xFA
115200
0.00%
192
EXTCLK / 8
11
0
0xF4
57600
0.00%
384
EXTCLK / 8
11
0
0xE8
28800
0.00%
768
EXTCLK / 8
11
0
0xD0
14400
0.00%
1536 EXTCLK / 8
11
0
0xA0
9600
0.00%
2304 EXTCLK / 8
11
0
0x70
X = Don’t care
*Note: SCA1-SCA0 and T1M bit definitions can be found in Section 23.1.
306
Rev. 1.4