C8051F124-GQR Datasheet, PDF (217/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 16.4. CCH0MA: Cache Miss Accumulator
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
CHMSOV
CHMSCTH
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x9A
SFR Page: F
Bit 7: CHMSOV: Cache Miss Penalty Overflow.
This bit indicates when the Cache Miss Penalty Accumulator has overflowed since it was
last written.
0: The Cache Miss Penalty Accumulator has not overflowed since it was last written.
1: An overflow of the Cache Miss Penalty Accumulator has occurred since it was last written.
Bits 6–0: CHMSCTH: Cache Miss Penalty Accumulator (bits 11–5)
These are bits 11-5 of the Cache Miss Penalty Accumulator. The next four bits (bits 4-1) are
stored in CHMSCTL in the CCH0TN register.
The Cache Miss Penalty Accumulator is incremented every clock cycle that the processor is
delayed due to a cache miss. This is primarily used as a diagnostic feature, when optimizing
code for execution speed.
Writing to CHMSCTH clears the lower 5 bits of the Cache Miss Penalty Accumulator.
Reading from CHMSCTH returns the current value of CHMSTCH, and latches bits 4-1 into
CHMSTCL so that they can be read. Because bit 0 of the Cache Miss Penalty Accumulator
is not available, the Cumulative Miss Penalty is equal to 2 * (CCHMSTCH:CCHMSTCL).
SFR Definition 16.5. FLSTAT: Flash Status
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
-
-
-
-
-
-
-
FLBUSY 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit
Addressable
SFR Address: 0x88
SFR Page: F
Bit 7–1:
Bit 0:
Reserved.
FLBUSY: Flash Busy
This bit indicates when a Flash write or erase operation is in progress.
0: Flash is idle or reading.
1: Flash write/erase operation is currently in progress.
Rev. 1.4
217