C8051F124-GQR Datasheet, PDF (58/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
5.2.2. Tracking Modes
The AD0TM bit in register ADC0CN controls the ADC0 track-and-hold mode. In its default state, the ADC0
input is continuously tracked when a conversion is not in progress. When the AD0TM bit is logic 1, ADC0
operates in low-power track-and-hold mode. In this mode, each conversion is preceded by a tracking
period of 3 SAR clocks (after the start-of-conversion signal). When the CNVSTR0 signal is used to initiate
conversions in low-power tracking mode, ADC0 tracks only when CNVSTR0 is low; conversion begins on
the rising edge of CNVSTR0 (see Figure 5.3). Tracking can also be disabled (shutdown) when the entire
chip is in low power standby or sleep modes. Low-power track-and-hold mode is also useful when AMUX
or PGA settings are frequently changed, to ensure that settling time requirements are met (see Section
“5.2.3. Settling Time Requirements” on page 59).
A. ADC Timing for External Trigger Source
CNVSTR0
(AD0CM[1:0]=10)
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ADC0TM=1
Low Power
or Convert
Track
ADC0TM=0 Track Or Convert
Convert
Convert
Low Power Mode
Track
B. ADC Timing for Internal Trigger Sources
Timer 2, Timer 3 Overflow;
Write '1' to AD0BUSY
(AD0CM[1:0]=00, 01, 11)
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
ADC0TM=1
Low Power
or Convert
Track
Convert
SAR Clocks
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Low Power Mode
ADC0TM=0
Track or
Convert
Convert
Track
Figure 5.3. ADC0 Track and Conversion Example Timing
58
Rev. 1.4