C8051F124-GQR Datasheet, PDF (285/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 20.1. SPI Slave Timing Parameters
Parameter
T_MCKH
T_MCKL
T_MIS
T_MIH
T_SE
T_SD
T_SEZ
T_SDZ
T_CKH
T_CKL
T_SIS
T_SIH
T_SOH
T_SLH
Description
Min
Master Mode Timing* (See Figure 20.8 and Figure 20.9)
SCK High Time
SCK Low Time
MISO Valid to SCK Shift Edge
1 x T_SYSCLK
1 x T_SYSCLK
1 x T_SYSCLK + 20
SCK Shift Edge to MISO Change
0
Slave Mode Timing* (See Figure 20.10 and Figure 20.11)
NSS Falling to First SCK Edge
Last SCK Edge to NSS Rising
2 x T_SYSCLK
2 x T_SYSCLK
NSS Falling to MISO Valid
NSS Rising to MISO High-Z
SCK High Time
SCK Low Time
MOSI Valid to SCK Sample Edge
SCK Sample Edge to MOSI Change
SCK Shift Edge to MISO Change
5 x T_SYSCLK
5 x T_SYSCLK
2 x T_SYSCLK
2 x T_SYSCLK
Last SCK Edge to MISO Change
(CKPHA = 1 ONLY)
6 x T_SYSCLK
*Note: T_SYSCLK is equal to one period of the device system clock (SYSCLK).
Max
Units
ns
ns
ns
ns
ns
ns
4 x T_SYSCLK ns
4 x T_SYSCLK ns
ns
ns
ns
ns
4 x T_SYSCLK ns
8 x T_SYSCLK ns
Rev. 1.4
285