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C8051F124-GQR Datasheet, PDF (233/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 17.1. AC Parameters for External Memory Interface
Parameter
TACS
TACW
TACH
TALEH
TALEL
TWDS
TWDH
TRDS
TRDH
Description
Address/Control Setup Time
Address/Control Pulse Width
Address/Control Hold Time
Address Latch Enable High Time
Address Latch Enable Low Time
Write Data Setup Time
Write Data Hold Time
Read Data Setup Time
Read Data Hold Time
Min
0
1 x TSYSCLK
0
1 x TSYSCLK
1 x TSYSCLK
1 x TSYSCLK
0
20
0
Note: TSYSCLK is equal to one period of the device system clock (SYSCLK).
Max
3 x TSYSCLK
16 x TSYSCLK
3 x TSYSCLK
4 x TSYSCLK
4 x TSYSCLK
19 x TSYSCLK
3 x TSYSCLK
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
—
ns
Rev. 1.4
233