C8051F124-GQR Datasheet, PDF (259/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
19. System Management Bus / I2C Bus (SMBus0)
The SMBus0 I/O interface is a two-wire, bi-directional serial bus. SMBus0 is compliant with the System
Management Bus Specification, version 1.1, and compatible with the I2C serial bus. Reads and writes to
the interface by the system controller are byte oriented with the SMBus0 interface autonomously control-
ling the serial transfer of the data. A method of extending the clock-low duration is available to accommo-
date devices with different speed capabilities on the same bus.
SMBus0 may operate as a master and/or slave, and may function on a bus with multiple masters. SMBus0
provides control of SDA (serial data), SCL (serial clock) generation and synchronization, arbitration logic,
and START/STOP control and generation.
SFR Bus
SMB0CN
BESSSAFT
UNT T I ATO
SSAO
EE
YM
B
SMB0STA
SSSSSSSS
TTTTTTTT
AAAAAAAA
76543210
SMB0CR
CCCCCCCC
RRRRRRRR
76543210
Clock Divide
Logic
SYSCLK
SMBUS
IRQ
Interrupt
Request
SMBUS CONTROL LOGIC
Arbitration
SCL Synchronization
Status Generation
SCL Generation (Master Mode)
IRQ Generation
Data Path
Control
SCL
Control
SDA
Control
BA
BA
7
SSSSSSS
LLLLLLL
V V V V V V VG
6 5 4 3 2 1 0C
SMB0ADR
0000000b
7 MSBs
8
SMB0DAT
76543210
8
Read
SMB0DAT
8
1
0
Write to
SMB0DAT
FILTER
SCL
N
C
R
O
S
S
B
A
R
FILTER
SDA
N
SFR Bus
Figure 19.1. SMBus0 Block Diagram
Port I/O
Rev. 1.4
259