C8051F124-GQR Datasheet, PDF (94/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
7.2.3. Settling Time Requirements
A minimum tracking time is required before an accurate conversion can be performed. This tracking time is
determined by the ADC2 MUX resistance, the ADC2 sampling capacitance, any external source resis-
tance, and the accuracy required for the conversion. Figure 7.3 shows the equivalent ADC2 input circuit.
The required ADC2 settling time for a given settling accuracy (SA) may be approximated by Equation 7.1.
Note: An absolute minimum settling time of 800 ns required after any MUX selection. In low-power tracking
mode, three SAR2 clocks are used for tracking at the start of every conversion. For most applications,
these three SAR2 clocks will meet the tracking requirements.
t
=
ln


S^-2---A^{n--}

R_TOTALC_SAMPLE
Equation 7.1. ADC2 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB)
t is the required settling time in seconds
R_TOTAL is the sum of the ADC2 MUX resistance and any external source resistance.
n is the ADC resolution in bits (8).
Differential Mode
MUX Select
Single-Ended Mode
MUX Select
AIN2.x
R_MUX = 5k
RC_Input= R_MUX * C_SAMPLE
AIN2.y
R_MUX = 5k
MUX Select
C_SAMPLE = 5pF
C_SAMPLE = 5pF
AIN2.x
R_MUX = 5k
RC_Input= R_MUX * C_SAMPLE
Note: When the PGA gain is set to 0.5, C_SAMPLE = 3pF
Figure 7.3. ADC2 Equivalent Input Circuit
C_SAMPLE = 5pF
94
Rev. 1.4