C8051F124-GQR Datasheet, PDF (134/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 11.1. PSBANK: Program Space Bank Select
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
COBANK
-
-
IFBANK
00010001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0xB1
SFR Page: All Pages
Bits 7–6: Reserved.
Bits 5–4: COBANK: Constant Operations Bank Select.
These bits select which Flash bank is targeted during constant operations (MOVC and Flash
MOVX) involving addresses 0x8000 to 0xFFFF. These bits are ignored when accessing the
Scratchpad memory areas (see Section “15. Flash Memory” on page 199).
00: Constant Operations Target Bank 0 (note that Bank 0 is also mapped between 0x0000 to
0x7FFF).
01: Constant Operations Target Bank 1.
10: Constant Operations Target Bank 2.
11: Constant Operations Target Bank 3.
Bits 3–2: Reserved.
Bits 1–0: IFBANK: Instruction Fetch Operations Bank Select.
These bits select which Flash bank is used for instruction fetches involving addresses 0x8000 to
0xFFFF. These bits can only be changed from code in Bank 0 (see Figure 11.3).
00: Instructions Fetch From Bank 0 (note that Bank 0 is also mapped between 0x0000 to
0x7FFF).
01: Instructions Fetch From Bank 1.
10: Instructions Fetch From Bank 2.
11: Instructions Fetch From Bank 3.
*Note: On the C8051F132/3, the COBANK and IFBANK bits should both remain set to the default setting of ‘01’ to
ensure proper device functionality.
Internal
Address IFBANK = 0
0xFFFF
IFBANK = 1
IFBANK = 2
IFBANK = 3
Bank 0
Bank 1
Bank 2
Bank 3
0x8000
0x7FFF
Bank 0
Bank 0
Bank 0
Bank 0
0x0000
Figure 11.3. Address Memory Map for Instruction Fetches (128 kB Flash Only)
134
Rev. 1.4