C8051F124-GQR Datasheet, PDF (315/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 23.3. CKCON: Clock Control
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
-
T1M
T0M
-
SCA1 SCA0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x8E
SFR Page: ₀
Bits7–5:
Bit4:
Bit3:
Bit2:
Bits1–0:
UNUSED. Read = 000b, Write = don’t care.
T1M: Timer 1 Clock Select.
This select the clock source supplied to Timer 1. T1M is ignored when C/T1 is set to logic 1.
0: Timer 1 uses the clock defined by the prescale bits, SCA1–SCA0.
1: Timer 1 uses the system clock.
T0M: Timer 0 Clock Select.
This bit selects the clock source supplied to Timer 0. T0M is ignored when C/T0 is set to
logic 1.
0: Counter/Timer 0 uses the clock defined by the prescale bits, SCA1-SCA0.
1: Counter/Timer 0 uses the system clock.
UNUSED. Read = 0b, Write = don’t care.
SCA1–SCA0: Timer 0/1 Prescale Bits
These bits control the division of the clock supplied to Timer 0 and/or Timer 1 if configured
to use prescaled clock inputs.
SCA1
SCA0
Prescaled Clock
0
0
0
1
1
0
1
1
System clock divided by 12
System clock divided by 4
System clock divided by 48
External clock divided by 8*
*Note: External clock divided by 8 is synchronized with the system
clock, and external clock must be less than or equal to the
system clock frequency to operate the timer in this mode.
SFR Definition 23.4. TL0: Timer 0 Low Byte
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits 7–0: TL0: Timer 0 Low Byte.
The TL0 register is the low byte of the 16-bit Timer 0.
R/W
R/W Reset Value
00000000
Bit1
Bit0
SFR Address: 0x8A
SFR Page: ₀
Rev. 1.4
315