C8051F124-GQR Datasheet, PDF (47/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 4.1. Pin Definitions (Continued)
Pin Numbers
Name
‘F120
‘F122
‘F124
‘F126
‘F121
‘F123
‘F125
‘F127
‘F130
‘F132
‘F131
‘F133
Type
Description
A8m/A0/P6.0 80
80
D I/O Bit 8 External Memory Address bus (Multiplexed
mode)
Bit 0 External Memory Address bus (Non-multi-
plexed mode)
Port 6.0
See Port Input/Output section for complete
description.
A9m/A1/P6.1 79
79
D I/O Port 6.1. See Port Input/Output section for com-
plete description.
A10m/A2/P6.2 78
78
D I/O Port 6.2. See Port Input/Output section for com-
plete description.
A11m/A3/P6.3 77
77
D I/O Port 6.3. See Port Input/Output section for com-
plete description.
A12m/A4/P6.4 76
76
D I/O Port 6.4. See Port Input/Output section for com-
plete description.
A13m/A5/P6.5 75
75
D I/O Port 6.5. See Port Input/Output section for com-
plete description.
A14m/A6/P6.6 74
74
D I/O Port 6.6. See Port Input/Output section for com-
plete description.
A15m/A7/P6.7 73
73
D I/O Port 6.7. See Port Input/Output section for com-
plete description.
AD0/D0/P7.0 72
72
D I/O Bit 0 External Memory Address/Data bus (Multi-
plexed mode)
Bit 0 External Memory Data bus (Non-multi-
plexed mode)
Port 7.0
See Port Input/Output section for complete
description.
AD1/D1/P7.1 71
71
D I/O Port 7.1. See Port Input/Output section for com-
plete description.
AD2/D2/P7.2 70
70
D I/O Port 7.2. See Port Input/Output section for com-
plete description.
AD3/D3/P7.3 69
69
D I/O Port 7.3. See Port Input/Output section for com-
plete description.
AD4/D4/P7.4 68
68
D I/O Port 7.4. See Port Input/Output section for com-
plete description.
Rev. 1.4
47