C8051F124-GQR Datasheet, PDF (185/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
14. Oscillators
The devices include a programmable internal oscillator and an external oscillator drive circuit. The internal
oscillator can be enabled, disabled, and calibrated using the OSCICN and OSCICL registers, as shown in
Figure 14.1. The system clock can be sourced by the external oscillator circuit, the internal oscillator, or the
on-chip phase-locked loop (PLL). The internal oscillator's electrical specifications are given in Table 14.1
on page 185.
Option 3
XTAL1
XTAL2
AV+
Option 4
XTAL1
Option 2
VDD
XTAL1
Option 1
XTAL1
XTAL2
OSCICL
OSCICN
CLKSEL
EN
Calibrated
Internal
Oscillator
Input
Circuit
OSC
n
00
SYSCLK
01
PLL
10
AGND
OSCXCN
Figure 14.1. Oscillator Diagram
Table 14.1. Oscillator Electrical Characteristics
–40°C to +85°C unless otherwise specified.
Parameter
Conditions
Calibrated Internal Oscillator
Frequency
Internal Oscillator Supply
Current (from V_DD)
OSCICN.7 = 1
External Clock Frequency
T_XCH (External Clock High Time)
T_XCL (External Clock Low Time)
Min Typ Max
24 24.5 25
— 400 —
0
— 30
15
—
—
15
—
—
Units
MHz
µA
MHz
ns
ns
14.1. Internal Calibrated Oscillator
All devices include a calibrated internal oscillator that defaults as the system clock after a system reset.
The internal oscillator period can be adjusted via the OSCICL register as defined by SFR Definition 14.1.
OSCICL is factory calibrated to obtain a 24.5 MHz frequency.
Rev. 1.4
185