C8051F124-GQR Datasheet, PDF (194/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 14.6. PLL0DIV: PLL Pre-divider
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W Reset Value
-
-
-
PLLM4 PLLM3 PLLM2 PLLM1 PLLM0 00000001
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x8D
SFR Page: F
Bits 7–5: UNUSED: Read = 000b; Write = don’t care.
Bits 4–0: PLLM4–0: PLL Reference Clock Pre-divider.
These bits select the pre-divide value of the PLL reference clock. When set to any non-zero
value, the reference clock will be divided by the value in PLLM4–0. When set to ‘00000b’,
the reference clock will be divided by 32.
SFR Definition 14.7. PLL0MUL: PLL Clock Scaler
R/W
PLLN7
Bit7
R/W
PLLN6
Bit6
R/W
PLLN5
Bit5
R/W
PLLN4
Bit4
R/W
PLLN3
Bit3
R/W
PLLN2
Bit2
R/W
PLLN1
Bit1
R/W Reset Value
PLLN0 00000001
Bit0
SFR Address: 0x8E
SFR Page: F
Bits 7–0: PLLN7–0: PLL Multiplier.
These bits select the multiplication factor of the divided PLL reference clock. When set to
any non-zero value, the multiplication factor will be equal to the value in PLLN7-0. When set
to ‘00000000b’, the multiplication factor will be equal to 256.
194
Rev. 1.4