C8051F124-GQR Datasheet, PDF (327/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Important Note About the PCA0CN Register: If the main PCA counter (PCA0H : PCA0L) overflows dur-
ing the execution phase of a read-modify-write instruction (bit-wise SETB or CLR, ANL, ORL, XRL) that
targets the PCA0CN register, the CF (Counter Overflow) bit will not be set. If the CF flag is used by soft-
ware to keep track of counter overflows, the following steps should be taken when performing a bit-wise
operation on the PCA0CN register:
Step 1. Disable global interrupts.
Step 2. Read PCA0L. This will latch the value of PCA0H.
Step 3. Read PCA0H, saving the value.
Step 4. Execute the bit-wise operation on CCFn (for example, CLR CCF0, or CCF0 = 0;).
Step 5. Read PCA0L.
Step 6. Read PCA0H, saving the value.
Step 7. If the value of PCA0H read in Step 3 is 0xFF and the value for PCA0H read in Step 6 is
0x00, then manually set the CF bit in software (for example, SETB CF, or CF = 1;).
Step 8. Re-enable interrupts.
Rev. 1.4
327