C8051F124-GQR Datasheet, PDF (255/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 18.15. P5: Port5 Data
R/W
P5.7
Bit7
R/W
P5.6
Bit6
R/W
P5.5
Bit5
R/W
P5.4
Bit4
R/W
P5.3
Bit3
R/W
P5.2
Bit2
R/W
P5.1
Bit1
R/W
Reset Value
P5.0 11111111
Bit0
Bit
Addressable
SFR Address: 0xD8
SFR Page: F
Bits7–0:
P5.[7:0]: Port5 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P5MDOUT bit = 0). See SFR Definition
18.16.
Read - Returns states of I/O pins.
0: P5.n pin is logic low.
1: P5.n pin is logic high.
Note:
P5.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-
multiplexed mode). See Section “17. External Data Memory Interface and On-Chip
XRAM” on page 219 for more information about the External Memory Interface.
SFR Definition 18.16. P5MDOUT: Port5 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits7–0: P5MDOUT.[7:0]: Port5 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
R/W
R/W
Reset Value
00000000
Bit1
Bit0
SFR Address: 0x9D
SFR Page: F
Rev. 1.4
255