C8051F124-GQR Datasheet, PDF (290/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
The Timer 1 overflow rate is determined by the Timer 1 clock source (T1CLK) and reload value (TH1). The
frequency of T1CLK is selected as described in Section “23.1. Timer 0 and Timer 1” on page 309. The
Timer 1 overflow rate is calculated as shown in Equation 21.2.
Equation 21.2. Timer 1 Overflow Rate
Timer1_OverflowRate = T1CLK  256 – TH1
When Timers 2, 3, or 4 are selected as a baud rate source, the baud rate is generated as shown in
Equation 21.3.
Equation 21.3. Mode 1 Baud Rate using Timer 2, 3, or 4
Mode1_BaudRate = 1  16  Timer234_OverflowRate
The overflow rate for Timer 2, 3, or 4 is determined by the clock source for the timer (TnCLK) and the 16-
bit reload value stored in the RCAPn register (n = 2, 3, or 4), as shown in Equation 21.4.
Equation 21.4. Timer 2, 3, or 4 Overflow Rate
Timer234_OverflowRate = TnCLK  65536 – RCAPn
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Rev. 1.4