C8051F124-GQR Datasheet, PDF (119/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
10. Comparators
Two on-chip programmable voltage comparators are included, as shown in Figure 10.1. The inputs of each
comparator are available at dedicated pins. The output of each comparator is optionally available at the
package pins via the I/O crossbar. When assigned to package pins, each comparator output can be pro-
grammed to operate in open drain or push-pull modes. See Section “18.1. Ports 0 through 3 and the
Priority Crossbar Decoder” on page 238 for Crossbar and port initialization details.
CP0+
CP0-
CP1+
CP1-
CP0RIE
CP0FIE
CP0MD1
CP0MD0
CP0EN
CP0OUT
CP0RIF
CP0FIF
CP0HYP1
CP0HYP0
CP0HYN1
CP0HYN0
CP0MD
AV+
Reset
Decision
Tree
+
D ^SET Q
D ^SET Q
-
Q
CLR
Q
CLR
AGND
(SYNCHRONIZER)
CP1RIE
CP1FIE
CP1MD1
CP1MD0
CP1EN
CP1OUT
CP1RIF
CP1FIF
CP1HYP1
CP1HYP0
CP1HYN1
CP1HYN0
CP1MD
AV+
+
D ^SET Q
D ^SET Q
-
Q
CLR
Q
CLR
AGND
(SYNCHRONIZER)
Figure 10.1. Comparator Functional Block Diagram
Crossbar
Interrupt
Handler
Crossbar
Interrupt
Handler
Rev. 1.4
119