C8051F124-GQR Datasheet, PDF (188/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 14.3. CLKSEL: System Clock Selection
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
-
CLKDIV1 CLKDIV0
-
-
CLKSL1 CLKSL0 00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x97
SFR Page: F
Bits 7–6: Reserved.
Bits 5–4: CLKDIV1–0: Output SYSCLK Divide Factor.
These bits can be used to pre-divide SYSCLK before it is output to a port pin through the
crossbar.
00: Output will be SYSCLK.
01: Output will be SYSCLK/2.
10: Output will be SYSCLK/4.
11: Output will be SYSCLK/8.
See Section “18. Port Input/Output” on page 235 for more details about routing this out-
put to a port pin.
Bits 3–2: Reserved.
Bits 1–0: CLKSL1–0: System Clock Source Select Bits.
00: SYSCLK derived from the Internal Oscillator, and scaled as per the IFCN bits in
OSCICN.
01: SYSCLK derived from the External Oscillator circuit.
10: SYSCLK derived from the PLL.
11: Reserved.
188
Rev. 1.4