C8051F124-GQR Datasheet, PDF (117/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
9.3. Reference Configuration on the C8051F130/1/2/3
On the C8051F130/1/2/3 devices, the VREF0 pin provides a voltage reference input for ADC0, which can
be connected to an external precision reference or the internal voltage reference, as shown in Figure 9.3.
The REF0CN register for the C8051F130/1/2/3 is described in SFR Definition 9.3.
External
Voltage
Reference
Circuit
VDD
R1
DGND
VREF0
Ref
ADC0
REF0CN
+
4.7F
VREF
0.1F
EN
Bias to ADC
x2
1.2V
Band-Gap
Recommended Bypass
Capacitors
Figure 9.3. Voltage Reference Functional Block Diagram (C8051F130/1/2/3)
SFR Definition 9.3. REF0CN: Reference Control (C8051F130/1/2/3)
SFR Page: 0
SFR Address: 0xD1
R/W
R/W
-
-
Bit7
Bit6
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
-
Reserved Reserved TEMPE BIASE REFBE 00000000
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bits7–5:
Bits4–3:
Bit2:
Bit1:
Bit0:
UNUSED. Read = 000b; Write = don’t care.
Reserved: Must be written to 0.
TEMPE: Temperature Sensor Enable Bit.
0: Internal Temperature Sensor Off.
1: Internal Temperature Sensor On.
BIASE: ADC/DAC Bias Generator Enable Bit. (Must be ‘1’ if using ADC or VREF).
0: Internal Bias Generator Off.
1: Internal Bias Generator On.
REFBE: Internal Reference Buffer Enable Bit.
0: Internal Reference Buffer Off.
1: Internal Reference Buffer On. Internal voltage reference is driven on the VREF pin.
Rev. 1.4
117