C8051F124-GQR Datasheet, PDF (44/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 4.1. Pin Definitions (Continued)
Pin Numbers
Name
‘F120
‘F122
‘F124
‘F126
‘F121
‘F123
‘F125
‘F127
‘F130
‘F132
‘F131
‘F133
Type
Description
AIN2.2/A10/P1.2 34 27 34 27 A In Port 1.2. See Port Input/Output section for com-
D I/O plete description.
AIN2.3/A11/P1.3 33 26 33 26 A In Port 1.3. See Port Input/Output section for com-
D I/O plete description.
AIN2.4/A12/P1.4 32 23 32 23 A In Port 1.4. See Port Input/Output section for com-
D I/O plete description.
AIN2.5/A13/P1.5 31 22 31 22 A In Port 1.5. See Port Input/Output section for com-
D I/O plete description.
AIN2.6/A14/P1.6 30 21 30 21 A In Port 1.6. See Port Input/Output section for com-
D I/O plete description.
AIN2.7/A15/P1.7 29 20 29 20 A In Port 1.7. See Port Input/Output section for com-
D I/O plete description.
A8m/A0/P2.0 46 37 46 37 D I/O Bit 8 External Memory Address bus (Multiplexed
mode)
Bit 0 External Memory Address bus (Non-multi-
plexed mode)
Port 2.0
See Port Input/Output section for complete
description.
A9m/A1/P2.1 45 36 45 36 D I/O Port 2.1. See Port Input/Output section for com-
plete description.
A10m/A2/P2.2 44 35 44 35 D I/O Port 2.2. See Port Input/Output section for com-
plete description.
A11m/A3/P2.3 43 34 43 34 D I/O Port 2.3. See Port Input/Output section for com-
plete description.
A12m/A4/P2.4 42 33 42 33 D I/O Port 2.4. See Port Input/Output section for com-
plete description.
A13m/A5/P2.5 41 32 41 32 D I/O Port 2.5. See Port Input/Output section for com-
plete description.
A14m/A6/P2.6 40 31 40 31 D I/O Port 2.6. See Port Input/Output section for com-
plete description.
A15m/A7/P2.7 39 30 39 30 D I/O Port 2.7. See Port Input/Output section for com-
plete description.
44
Rev. 1.4