C8051F124-GQR Datasheet, PDF (206/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
The Flash Access Limit security feature (see SFR Definition 15.1) protects proprietary program code and
data from being read by software running on the device. This feature provides support for OEMs that wish
to program the MCU with proprietary value-added firmware before distribution. The value-added firmware
can be protected while allowing additional code to be programmed in remaining program memory space
later.
The Flash Access Limit (FAL) is a 17-bit address that establishes two logical partitions in the program
memory space. The first is an upper partition consisting of all the program memory locations at or above
the FAL address, and the second is a lower partition consisting of all the program memory locations start-
ing at 0x00000 up to (but excluding) the FAL address. Software in the upper partition can execute code in
the lower partition, but is prohibited from reading locations in the lower partition using the MOVC instruc-
tion. (Executing a MOVC instruction from the upper partition with a source address in the lower partition
will return indeterminate data.) Software running in the lower partition can access locations in both the
upper and lower partition without restriction.
The Value-added firmware should be placed in the lower partition. On reset, control is passed to the value-
added firmware via the reset vector. Once the value-added firmware completes its initial execution, it
branches to a predetermined location in the upper partition. If entry points are published, software running
in the upper partition may execute program code in the lower partition, but it cannot read or change the
contents of the lower partition. Parameters may be passed to the program code running in the lower parti-
tion either through the typical method of placing them on the stack or in registers before the call or by plac-
ing them in prescribed memory locations in the upper partition.
The FAL address is specified using the contents of the Flash Access Limit Register. The 8 MSBs of the 17-
bit FAL address are determined by the setting of the FLACL register. Thus, the FAL can be located on 512-
byte boundaries anywhere in program memory space. However, the 1024-byte erase sector size essen-
tially requires that a 1024 boundary be used. The contents of a non-initialized FLACL security byte are
0x00, thereby setting the FAL address to 0x00000 and allowing read access to all locations in program
memory space by default.
SFR Definition 15.1. FLACL: Flash Access Limit
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0 SFR Address:
SFR Address: 0xB7
SFR Page: F
Bits 7–0: FLACL: Flash Access Limit.
This register holds the most significant 8 bits of the 17-bit program memory read/write/erase
limit address. The lower 9 bits of the read/write/erase limit are always set to 0. A write to this
register sets the Flash Access Limit. This register can only be written once after any reset.
Any subsequent writes are ignored until the next reset. To fully protect all addresses
below this limit, bit 0 of FLACL should be set to ‘0’ to align the FAL on a 1024-byte
Flash page boundary.
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Rev. 1.4