C8051F124-GQR Datasheet, PDF (6/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
17.5.3.Split Mode with Bank Select................................................................... 225
17.5.4.External Only.......................................................................................... 225
17.6.EMIF Timing ................................................................................................... 225
17.6.1.Non-multiplexed Mode ........................................................................... 227
17.6.2.Multiplexed Mode ................................................................................... 230
18. Port Input/Output.................................................................................................. 235
18.1.Ports 0 through 3 and the Priority Crossbar Decoder..................................... 238
18.1.1.Crossbar Pin Assignment and Allocation ............................................... 238
18.1.2.Configuring the Output Modes of the Port Pins...................................... 239
18.1.3.Configuring Port Pins as Digital Inputs................................................... 240
18.1.4.Weak Pullups ......................................................................................... 240
18.1.5.Configuring Port 1 Pins as Analog Inputs .............................................. 240
18.1.6.External Memory Interface Pin Assignments ......................................... 241
18.1.7.Crossbar Pin Assignment Example........................................................ 243
18.2.Ports 4 through 7 (100-pin TQFP devices only) ............................................. 252
18.2.1.Configuring Ports which are not Pinned Out .......................................... 252
18.2.2.Configuring the Output Modes of the Port Pins...................................... 252
18.2.3.Configuring Port Pins as Digital Inputs................................................... 253
18.2.4.Weak Pullups ......................................................................................... 253
18.2.5.External Memory Interface ..................................................................... 253
19. System Management Bus / I2C Bus (SMBus0) .................................................. 259
19.1.Supporting Documents ................................................................................... 260
19.2.SMBus Protocol.............................................................................................. 260
19.2.1.Arbitration............................................................................................... 261
19.2.2.Clock Low Extension.............................................................................. 261
19.2.3.SCL Low Timeout................................................................................... 261
19.2.4.SCL High (SMBus Free) Timeout .......................................................... 261
19.3.SMBus Transfer Modes.................................................................................. 262
19.3.1.Master Transmitter Mode ....................................................................... 262
19.3.2.Master Receiver Mode ........................................................................... 262
19.3.3.Slave Transmitter Mode ......................................................................... 263
19.3.4.Slave Receiver Mode ............................................................................. 263
19.4.SMBus Special Function Registers ................................................................ 264
19.4.1.Control Register ..................................................................................... 264
19.4.2.Clock Rate Register ............................................................................... 267
19.4.3.Data Register ......................................................................................... 268
19.4.4.Address Register.................................................................................... 268
19.4.5.Status Register....................................................................................... 269
20. Enhanced Serial Peripheral Interface (SPI0)...................................................... 273
20.1.Signal Descriptions......................................................................................... 274
20.1.1.Master Out, Slave In (MOSI).................................................................. 274
20.1.2.Master In, Slave Out (MISO).................................................................. 274
20.1.3.Serial Clock (SCK) ................................................................................. 274
20.1.4.Slave Select (NSS) ................................................................................ 274
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Rev. 1.4