C8051F124-GQR Datasheet, PDF (73/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
6. ADC0 (10-Bit ADC, C8051F122/3/6/7 and C8051F13x Only)
The ADC0 subsystem for the C8051F122/3/6/7 and C8051F13x consists of a 9-channel, configurable ana-
log multiplexer (AMUX0), a programmable gain amplifier (PGA0), and a 100 ksps, 10-bit successive-
approximation-register ADC with integrated track-and-hold and Programmable Window Detector (see
block diagram in Figure 6.1). The AMUX0, PGA0, Data Conversion Modes, and Window Detector are all
configurable under software control via the Special Function Registers shown in Figure 6.1. The voltage
reference used by ADC0 is selected as described in Section “9. Voltage Reference” on page 113. The
ADC0 subsystem (ADC0, track-and-hold and PGA0) is enabled only when the AD0EN bit in the ADC0
Control register (ADC0CN) is set to logic 1. The ADC0 subsystem is in low power shutdown when this bit is
logic 0.
AIN0.0
AIN0.1
AIN0.2
AIN0.3
AIN0.4
AIN0.5
AIN0.6
AIN0.7
ADC0GTH
ADC0GTL
ADC0LTH
ADC0LTL
20 Comb.
Logic
+
AV+
10
-
AD0EN
+
AV+
- 9-to-1
+ ^AMUX
(SE or
- ^DIFF)
+
-
X
+
-
AGND
10-Bit
SAR
10
ADC
AD0WINT
TEMP
SENSOR
AGND
00
Start Conversion ⁰¹
10
11
AD0BUSY (W)
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
AMX0CF
AMX0SL
ADC0CF
ADC0CN
Figure 6.1. 10-Bit ADC0 Functional Block Diagram
6.1. Analog Multiplexer and PGA
Eight of the AMUX channels are available for external measurements while the ninth channel is internally
connected to an on-chip temperature sensor (temperature transfer function is shown in Figure 6.2). AMUX
input pairs can be programmed to operate in either differential or single-ended mode. This allows the user
to select the best measurement technique for each input channel, and even accommodates mode
changes "on-the-fly". The AMUX defaults to all single-ended inputs upon reset. There are two registers
associated with the AMUX: the Channel Selection register AMX0SL (SFR Definition 6.2), and the Configu-
ration register AMX0CF (SFR Definition 6.1). The table in SFR Definition 6.2 shows AMUX functionality by
channel, for each possible configuration. The PGA amplifies the AMUX output signal by an amount deter-
mined by the states of the AMP0GN2-0 bits in the ADC0 Configuration register, ADC0CF (SFR Definition
6.3). The PGA can be software-programmed for gains of 0.5, 2, 4, 8 or 16. Gain defaults to unity on reset.
Rev. 1.4
73