C8051F124-GQR Datasheet, PDF (196/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 14.3. PLL Lock Timing Characteristics
–40 to +85 °C unless otherwise specified
Input
Multiplier
Pll0flt
Output
Min Typ Max
Frequency
(Pll0mul)
Setting
Frequency
20
0x0F
100 MHz
202
13
0x0F
65 MHz
115
16
0x1F
80 MHz
241
5 MHz
9
12
0x1F
0x2F
45 MHz
60 MHz
116
258
6
0x2F
30 MHz
112
10
0x3F
50 MHz
263
5
0x3F
25 MHz
113
4
0x01
100 MHz
42
2
0x01
50 MHz
33
3
0x11
75 MHz
48
25 MHz
2
2
0x11
0x21
50 MHz
50 MHz
17
42
1
0x21
25 MHz
33
2
0x31
50 MHz
60
1
0x31
25 MHz
25
Units
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
196
Rev. 1.4