C8051F124-GQR Datasheet, PDF (257/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 18.19. P7: Port7 Data
R/W
P7.7
Bit7
R/W
P7.6
Bit6
R/W
P7.5
Bit5
R/W
P7.4
Bit4
R/W
P7.3
Bit3
R/W
P7.2
Bit2
R/W
P7.1
Bit1
R/W
Reset Value
P7.0 11111111
Bit0
Bit
Addressable
SFR Address: 0xF8
SFR Page: F
Bits7–0:
P7.[7:0]: Port7 Output Latch Bits.
Write - Output appears on I/O pins.
0: Logic Low Output.
1: Logic High Output (Open-Drain if corresponding P7MDOUT bit = 0). See SFR Definition
18.20.
Read - Returns states of I/O pins.
0: P7.n pin is logic low.
1: P7.n pin is logic high.
Note:
P7.[7:0] can be driven by the External Data Memory Interface (as AD[7:0] in Multiplexed
mode, or as D[7:0] in Non-multiplexed mode). See Section “17. External Data Memory
Interface and On-Chip XRAM” on page 219 for more information about the External Memory
Interface.
SFR Definition 18.20. P7MDOUT: Port7 Output Mode
R/W
R/W
R/W
R/W
R/W
R/W
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits7–0: P7MDOUT.[7:0]: Port7 Output Mode Bits.
0: Port Pin output mode is configured as Open-Drain.
1: Port Pin output mode is configured as Push-Pull.
R/W
R/W
Reset Value
00000000
Bit1
Bit0
SFR Address: 0x9F
SFR Page: F
Rev. 1.4
257