C8051F124-GQR Datasheet, PDF (205/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Read and Write/Erase Security Bits.
(Bit 7 is MSB.)
Bit Memory Block
7
N/A
6
N/A
5
N/A
4
N/A
3 0x0C000 - 0x0FFFF
2 0x08000 - 0x0BFFF
1 0x04000 - 0x07FFF
0 0x00000 - 0x03FFF
SFLE = 0
Read Lock Byte
Write/Erase Lock Byte
0x0FFFF
0x0FFFE
0x0FFFD
Flash Access Limit
SFLE = 1
Program/Data
Memory Space
0x00000
Scratchpad Memory
(Data only)
0x00FF
0x0000
Flash Read Lock Byte
Bits7–0: Each bit locks a corresponding block of memory. (Bit7 is MSB).
0: Read operations are locked (disabled) for corresponding block across the JTAG interface.
1: Read operations are unlocked (enabled) for corresponding block across the JTAG inter-
face.
Flash Write/Erase Lock Byte
Bits7–0: Each bit locks a corresponding block of memory.
0: Write/Erase operations are locked (disabled) for corresponding block across the JTAG
interface.
1: Write/Erase operations are unlocked (enabled) for corresponding block across the JTAG
interface.
NOTE: When the highest block is locked, the security bytes may be written but not erased.
Flash access Limit Register (FLACL)
The Flash Access Limit is defined by the setting of the FLACL register, as described in SFR
Definition 15.1. Firmware running at or above this address is prohibited from using the
MOVX and MOVC instructions to read, write, or erase Flash locations below this address.
Figure 15.3. 64 kB Flash Memory Map and Security Bytes
Rev. 1.4
205