C8051F124-GQR Datasheet, PDF (40/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Table 3.2. Global DC Electrical Characteristics (C8051F124/5/6/7)
–40 to +85 °C, 50 MHz System Clock unless otherwise specified.
Parameter
Conditions
Min
Typ
Max Units
Analog Supply Voltage¹
2.7
3.0
3.6
V
Analog Supply Current
Internal REF, ADC, DAC, Com-
—
1.7
—
mA
parators all active
Analog Supply Current with Internal REF, ADC, DAC, Com-
—
0.2
—
µA
analog sub-systems inactive parators all disabled, oscillator
disabled
Analog-to-Digital Supply
Delta (|V_DD – AV+|)
—
—
0.5
V
Digital Supply Voltage
2.7
3.0
3.6
V
Digital Supply Current with
CPU active
V_DD = 3.0 V, Clock = 50 MHz
V_DD = 3.0 V, Clock = 1 MHz
V_DD = 3.0 V, Clock = 32 kHz
Digital Supply Current with V_DD = 3.0 V, Clock = 50 MHz
CPU inactive (not accessing _{VDD = 3.0 V, Clock = 1 MHz}
Flash)
V_DD = 3.0 V, Clock = 32 kHz
Digital Supply Current (shut- Oscillator not running
down)
Digital Supply RAM Data
Retention Voltage
—
35
—
mA
1
mA
33
µA
—
27
—
mA
0.4
mA
15
µA
—
0.4
—
µA
—
1.5
—
V
SYSCLK (System Clock)^2,3
0
—
50
MHz
Specified Operating
Temperature Range
–40
—
+85
°C
Notes:
1. Analog Supply AV+ must be greater than 1 V for V_DD monitor to operate.
2. SYSCLK is the internal device clock. For operational speeds in excess of 30 MHz, SYSCLK must be derived
from the phase-locked loop (PLL).
3. SYSCLK must be at least 32 kHz to enable debugging.
40
Rev. 1.4