C8051F124-GQR Datasheet, PDF (46/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Name
ALE/P4.5
RD/P4.6
WR/P4.7
A8/P5.0
A9/P5.1
A10/P5.2
A11/P5.3
A12/P5.4
A13/P5.5
A14/P5.6
A15/P5.7
Table 4.1. Pin Definitions (Continued)
Pin Numbers
‘F120
‘F122
‘F124
‘F126
‘F121
‘F123
‘F125
‘F127
‘F130
‘F132
‘F131
‘F133
Type
Description
93
93
D I/O ALE Strobe for External Memory Address bus
(multiplexed mode)
Port 4.5
See Port Input/Output section for complete
description.
92
92
D I/O /RD Strobe for External Memory Address bus
Port 4.6
See Port Input/Output section for complete
description.
91
91
D I/O /WR Strobe for External Memory Address bus
Port 4.7
See Port Input/Output section for complete
description.
88
88
D I/O Bit 8 External Memory Address bus (Non-multi-
plexed mode)
Port 5.0
See Port Input/Output section for complete
description.
87
87
D I/O Port 5.1. See Port Input/Output section for com-
plete description.
86
86
D I/O Port 5.2. See Port Input/Output section for com-
plete description.
85
85
D I/O Port 5.3. See Port Input/Output section for com-
plete description.
84
84
D I/O Port 5.4. See Port Input/Output section for com-
plete description.
83
83
D I/O Port 5.5. See Port Input/Output section for com-
plete description.
82
82
D I/O Port 5.6. See Port Input/Output section for com-
plete description.
81
81
D I/O Port 5.7. See Port Input/Output section for com-
plete description.
46
Rev. 1.4