C8051F124-GQR Datasheet, PDF (39/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
3. Global DC Electrical Characteristics
Table 3.1. Global DC Electrical Characteristics
(C8051F120/1/2/3 and C8051F130/1/2/3)
–40 to +85 °C, 100 MHz System Clock unless otherwise specified.
Parameter
Analog Supply Voltage¹
Conditions
SYSCLK = 0 to 50 MHz
SYSCLK > 50 MHz
Min
Typ
Max Units
2.7
3.0
3.6
V
3.0
3.3
3.6
V
Analog Supply Current
Internal REF, ADCs, DACs, Com- _—
1.7
—
mA
parators all active
Analog Supply Current with Internal REF, ADCs, DACs, Com- _—
0.2
—
µA
analog sub-systems inactive parators all disabled, oscillator
disabled
Analog-to-Digital Supply
Delta (|V_DD – AV+|)
Digital Supply Voltage
SYSCLK = 0 to 50 MHz
SYSCLK > 50 MHz
—
—
0.5
V
2.7
3.0
3.6
V
3.0
3.3
3.6
V
Digital Supply Current with
CPU active
Digital Supply Current with
CPU inactive (not accessing
Flash)
Digital Supply Current (shut-
down)
Digital Supply RAM Data
Retention Voltage
SYSCLK (System Clock)^2,3
V_DD = 3.0 V, Clock = 100 MHz
V_DD = 3.0 V, Clock = 50 MHz
V_DD = 3.0 V, Clock = 1 MHz
V_DD = 3.0 V, Clock = 32 kHz
V_DD = 3.0 V, Clock = 100 MHz
V_DD = 3.0 V, Clock = 50 MHz
V_DD = 3.0 V, Clock = 1 MHz
V_DD = 3.0 V, Clock = 32 kHz
Oscillator not running
V_DD, AV+ = 2.7 to 3.6 V
V_DD, AV+ = 3.0 to 3.6 V
—
65
—
mA
35
mA
1
mA
33
µA
—
40
—
mA
20
mA
0.4
mA
15
µA
—
0.4
—
µA
—
1.5
—
V
0
—
50
MHz
0
100
MHz
Specified Operating Temper-
ature Range
–40
—
+85
°C
Notes:
1. Analog Supply AV+ must be greater than 1 V for V_DD monitor to operate.
2. SYSCLK is the internal device clock. For operational speeds in excess of 30 MHz, SYSCLK must be derived
from the Phase-Locked Loop (PLL).
3. SYSCLK must be at least 32 kHz to enable debugging.
Rev. 1.4
39