C8051F124-GQR Datasheet, PDF (174/350 Pages) Silicon Laboratories – Mixed Signal ISP Flash MCU Family

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
SFR Definition 12.10. MAC0ACC0: MAC0 Accumulator Byte 0
R
R
R
R
R
R
R
R
Reset Value
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address: 0x93
SFR Page: 3
Bits 7–0: Byte 0 (bits 7–0) of MAC0 Accumulator.
*Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 12.11. MAC0OVR: MAC0 Accumulator Overflow
R
R
R
R
R
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits 7–0: MAC0 Accumulator Overflow Bits (bits 39–32).
R
R
Reset Value
00000000
Bit1
Bit0
SFR Address: 0x97
SFR Page: 3
*Note: The contents of this register should not be changed by software during the first two MAC0 pipeline stages.
SFR Definition 12.12. MAC0RNDH: MAC0 Rounding Register High Byte
R
R
R
R
R
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bits 7–0: High Byte (bits 15–8) of MAC0 Rounding Register.
R
R
Reset Value
00000000
Bit1
Bit0
SFR Address: 0xCF
SFR Page: 3
174
Rev. 1.4