M16C80 Datasheet, PDF (99/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
11. DMAC
(2) DMAC transfer cycles
Any combination of even or odd transfer read and write addresses is possible. Table 11.2 shows the
number of DMAC transfer cycles.
The number of DMAC transfer cycles can be calculated as follows:
No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k
Table 11.2 No. of DMAC transfer cycles
Transfer unit
8-bit transfers
(BWi = “0”)
16-bit transfers
(BWi = “1”)
Bus width
16-bit
(DSi = “1”)
8-bit
(DSi = “0”)
16-bit
(DSi = “1”)
8-bit
(DSi = “0”)
Access address ^{Single-chip mode}
Memory expansion mode
Microprocessor mode
No. of read No. of write No. of read No. of write
cycles
cycles
cycles
cycles
Even
1
1
1
1
Odd
1
1
1
1
Even
—
—
1
1
Odd
—
—
1
1
Even
1
1
1
1
Odd
2
2
2
2
Even
—
—
2
2
Odd
—
—
2
2
Coefficient j, k
Internal Memory
Internal ROM/RAM SFR area
No wait With wait
j=1
j=2
j=2
k=1
k=2
k=2
No wait
j=1
k=2
External Memory
Separate bus
One wait Two waits Three waits
j=2
j=3
j=4
k=2
k=3
k=4
Multiplex bus
Two waits Three waits
j=3
j=4
k=3
k=4
DMA Request Bit
The DMAC can issue DMA requests using preselected DMA request factors for each channel as trig-
gers.
The DMA transfer request factors include the reception of DMA request signals from the internal periph-
eral functions, software DMA factors generated by the program, and external factors using input from
external interrupt signals.
See the description of the DMAi factor selection register for details of how to select DMA request factors.
DMA requests are received as DMA requests when the DMAi request bit is set to “1” and the channel i
transfer mode select bits are “01” or “11”. Therefore, even if the DMAi request bit is “1”, no DMA request
is received if the channel i transfer mode select bit is “00”. In this case, DMAi request bit is cleared.
Because the channel i transfer mode select bits default to “00” after a reset, remember to set the channel
i transfer mode select bit for the channel to be activated after setting the DMAC related registers. This
enables receipt of the DMA requests for that channel, and DMA transfers are then performed when the
DMAi request bit is set.
The following describes when the DMAi request bit is set and cleared.
Rev.1.00 Aug. 02, 2005 ^{Page 88} of 329
REJ09B0187-0100