M16C80 Datasheet, PDF (79/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
9.13 Changes of IPL When Interrupt Request Acknowledged
When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is
set to the processor interrupt priority level (IPL).
If an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in
Table 9.7 is set to the IPL.
Table 9.7 Relationship between Interrupts without Interrupt Priority Levels and IPL
Interrupt sources without interrupt priority levels
_______
Watchdog timer, NMI
Value that is set to IPL
7
Reset
0
Other
Not changed
9.14 Saving Registers
In an interrupt sequence, only the contents of the flag register (FLG) and program counter (PC) are
saved to the stack area.
The order in which these contents are saved is as follows: First, the FLG register is saved to the stack
area. Next, the 16 high-order bits and 16 low-order bits of the program counter expanded to 32-bit are
saved. Figure 9.6 shows the stack status before an interrupt request is acknowledged and the stack
status after an interrupt request is acknowledged.
In a high-speed interrupt sequence, the contents of the flag register (FLG) is saved to the flag save
register (SVF) and program counter (PC) is saved to PC save register (SVP).
If there are any other registers you want to be saved, save them in software at the beginning of the
interrupt routine. The PUSHM instruction allows you to save all registers except the stack pointer (SP)
by a single instruction.
The execution speed is improved when register bank 1 is used with high speed interrupt register selected
by not saving registers to the stack but to the switching register bank. In this case, switch register bank
mode for high-speed interrupt routine.
Address
Stack area
MSB
LSB
Address
Stack area
MSB
LSB
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
Content of
previous stack
Content of
previous stack
[SP]
Stack pointer
value before
interrupt occurs
m-6
m-5
m–4
m–3
m–2
m–1
m
m+1
Program counter
(PCL)
Program counter
(PCM)
Program counter
(PCH)
00
Flag register
(FLGL)
Flag register
(FLGH)
Content of
previous stack
Content of
previous stack
[SP]
New stack
pointer value
Stack status before interrupt request is acknowledged
Stack status after interrupt request is acknowledged
Figure 9.6 Stack status before and after an interrupt request is acknowledged
Rev.1.00 Aug. 02, 2005 ^{Page 68} of 329
REJ09B0187-0100