M16C80 Datasheet, PDF (56/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
8. Clock Generating Circuit
The following paragraphs describes the clocks generated by the clock generating circuit.
(1) Main clock
The main clock is generated by the main clock oscillation circuit. After a reset, the clock is divided by 8 to
the BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 000616). Switching to
the sub clock oscillation as CPU operating clock source before stopping the clock reduces the power
dissipation.
When the main clock is stoped (bit 5 at address 000616 =1) or the mode is shifted to stop mode (bit 0 at
address 000716 =1), the main clock division register (address 000C16) is set to the division by 8 ("0816").
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock
oscillation circuit can be reduced using the XIN-XOUT drive capacity select bit (bit 5 at address 000716).
Reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. This bit
defaults to “1” when shifting from high-speed or middle-speed mode to stop mode and after a reset.
This bit remains in low-speed and low power dissipation mode.
(2) Sub clock
The sub clock is generated by the sub clock oscillation circuit. No sub clock is generated after a reset.
After oscillation is started using the port Xc select bit (bit 4 at address 000616), the sub clock can be
selected as the BCLK by using the system clock select bit (bit 7 at address 000616). However, be sure
that the sub clock oscillation has fully stabilized before switching.
After the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the sub clock
oscillation circuit can be reduced using the XCIN-XCOUT drive capacity select bit (bit 3 at address 000616).
Reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation. This bit
changes to “1” when shifting to stop mode and at a reset.
When the sub clock is used, set ports P86 and P87 to no pull-up resistance with the input port.
(3) BCLK
The BCLK is the clock that drives the CPU, and is either fc or is derived by dividing the main clock by 1,
2, 3, 4, 6, 8, 10, 12, 14 or 16. The BCLK is derived by dividing the main clock by 8 after a reset.
This signal is output from BCLK pin using CM01, CM00 and PM07 in memory expansion mode and
microprocessor mode.
When main clock is stoped or shifting to stop mode, the main clock division register (address 000C16) is
set to the division by 8 ("0816").
(4) Peripheral function clock
• f1, f8, f32, f1SIO2, f8SIO2, f32SIO2
The clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. The
peripheral function clock is stopped by stopping the main clock or by setting the WAIT peripheral function
clock stop bit (bit 2 at 000616) to “1” and then executing a WAIT instruction.
• fAD
This clock has the same frequency as the main clock and is used for A/D conversion.
(5) fC32
This clock is derived by dividing the sub clock by 32. It is used for the timer A and timer B counts.
(6) fC
This clock has the same frequency as the sub clock. It is used for BCLK and for the watchdog timer.
Figure 8.4 shows the system clock control registers 0 and 1 and Figure 8.5 shows main clock division
register.
Rev.1.00 Aug. 02, 2005 ^{Page 45} of 329
REJ09B0187-0100