M16C80 Datasheet, PDF (69/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
9. Interrupt Outline
9.3 Hardware Interrupts
There are Two types in hardware Interrupts; special interrupts and Peripheral I/O interrupts.
(1) Special interrupts
Special interrupts are nonmaskable interrupts.
• Reset
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A reset occurs when the RESET pin is pulled low.
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• NMI interrupt
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This interrupt occurs when the NMI pin is pulled low.
• Watchdog timer interrupt
This interrupt is caused by the watchdog timer.
• Address-match interrupt
This interrupt occurs immediately before the instruction at the address indicated by the address match
interrupt register is executed while the address match interrupt enable bit is set to “1”.
This interrupt does not occur if any address other than the start address of an instruction is set in the
address match register.
• Single-step interrupt
This interrupt is used exclusively for debugger purposes, do not use it in other circumstances. A single-
step interrupt occurs when the D flag is set (= 1); in this case, an interrupt is generated after one
instruction is executed.
(2) Peripheral I/O interrupts
A peripheral I/O interrupt is generated by one of built-in peripheral functions. Built-in peripheral func-
tions are dependent on classes of products, so the interrupt factors too are dependent on classes of
products. The interrupt vector table is the same as the one for software interrupt numbers 0 through
43 the INT instruction uses. Peripheral I/O interrupts are maskable interrupts.
• Bus collision detection, start/stop condition detection interrupts (UART2, UART3, UART4), fault
error interrupts (UART3, 4)
This is an interrupt that the serial I/O bus collision detection generates. When I2C mode is selected,
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start, stop condition interrupt is selected. When SS pin is selected, fault error interrupt is selected.
• DMA0 through DMA3 interrupts
These are interrupts that DMA generates.
• Key-input interrupt
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A key-input interrupt occurs if an “L” is input to the KI pin.
• A/D conversion interrupt
This is an interrupt that the A/D converter generates.
• UART0, UART1, UART2/NACK, UART3/NACK and UART4/NACK transmission interrupt
These are interrupts that the serial I/O transmission generates.
• UART0, UART1, UART2/ACK, UART3/ACK and UART4/ACK reception interrupt
These are interrupts that the serial I/O reception generates.
• Timer A0 interrupt through timer A4 interrupt
These are interrupts that timer A generates
• Timer B0 interrupt through timer B5 interrupt
These are interrupts that timer B generates.
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• INT0 interrupt through INT5 interrupt
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An INT interrupt selects a edge sense or a level sense. In edge sense, an INT interrupt occurs if either
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a rising edge or a falling edge or a both edge is input to the INT pin. In level sense, an INT interrupt
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occurs if either an "H" level or an "L" level is input to the INT pin.
Rev.1.00 Aug. 02, 2005 ^{Page 58} of 329
REJ09B0187-0100