M16C80 Datasheet, PDF (171/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
20. UARTi Special Mode Register (i = 2 to 4)
UARTi Special Mode Register 2(i=2 to 4) (Address 033616,032616,02F616)
Bit 0 is the IIC mode select bit 2. Table 20.2 gives control changes by bit when the IIC mode select bit
is “1”. Start and stop condition detection timing characteristics are shown in Figure 20.4. Always set bit
7 (start/stop condition control bit) to “1”.
Bit 1 is the clock synchronization bit. When this bit is set to “1”, if the rise edge is detected at pin SCLi
while the internal SCL is H level, the internal SCL is changed to L level, the UARTi bit rate generator
value is reloaded and the L sector count starts. Also, while the SCLi pin is L level, if the internal SCL
changes from L level to H, the count stops. If the SCLi pin is H level, counting restarts. Because of this
function, the UARTi transmission-reception clock takes the AND condition for the internal SCL and
SCLi pin signals. This function operates from the clock half period before the 1st rise of the UARTi
clock to the 9th rise. To use this function, select the internal clock as the transfer clock.
Bit 2 is the SCL wait output bit. When this bit is set to “1”, output from the SCLi pin is fixed to L level at
the clock’s 9th rise. When set to “0”, the L output lock is released.
Bit 3 is the SDA output stop bit. When this bit is set to “1”, an arbitration lost is generated. If the
arbitration lost detection flag is “1”, the SDAi pin simultaneously becomes high impedance.
Bit 4 is the UARTi initialize bit. While this bit is set to “1”, the following operations are performed when
the start condition is detected.
1. The transmission shift register is initialized and the content of the transmission register is trans-
mitted to the transmission shift register. As such, transmission starts with the 1st bit of the next
input clock. However, the UARTi output value remains the same as when the start condition was
detected, without changing from when the clock is input to when the 1st bit of data is output.
2. The reception shift register is initialized and reception starts with the 1st bit of the next input
clock.
3. The SCL wait output bit is set to “1”. As such, the SCLi pin becomes L level at the rise of the 9th
bit of the clock.
When UART transmission-reception has been started using this function, the content of the transmis-
sion buffer available flag does not change. Also, to use this function, select an external clock as the
transfer clock.
Bit 5 is SCL wait output bit 2. When this bit is set to “1” and serial I/O has been selected, an L level can
be forcefully output from the SCLi pin even during UART operation. When this bit is set to “0', the L
output from the SCLi pin is canceled and the UARTi clock is input and output.
Bit 6 is the SDA output disable bit. When this bit is set to “1”, the SDAi pin is forcefully made high
impedance. To overwrite this bit, do so at the rise of the UARTi transfer clock. The arbitration lost
detection flag may be set.
Rev.1.00 Aug. 02, 2005 ^{Page 160} of 329
REJ09B0187-0100