M16C80 Datasheet, PDF (173/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
20. UARTi Special Mode Register (i = 2 to 4)
(2) Serial Interface Special Function
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UART 3 and UART4 can control communications on the serial bus using the SSi input pins (Figure 20.5).
The master outputting the transfer clock transfers data to the slave inputting the transfer clock. In this
case, in order to prevent a data collision on the bus, the master floats the output pin of other slaves/
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masters using the SSi input pins. Figure 20.6 shows the structure of UARTi special mode register 3
(addresses 032516 and 02F516 [i = 3 or 4]) which controls this mode.
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SSi input pins function between the master and slave are as follows.
IC1
P13
P12
P93(SS3)
P90(CLK3)
P91(RxD3)
P92(TxD3)
M16C/80 (M)
IC2
P93(SS3)
P90(CLK3)
P91(STxD3)
P92(SRxD3)
M16C/80 (S)
IC3
M :Master
S :Slave
P93(SS3)
P90(CLK3)
P91(STxD3)
P92(SRxD3)
M16C/80 (S)
Figure 20.5 Serial bus communication control example using the SSi input pins
< Slave Mode (STxDi and SRxDi are selected, DINC = 1) >
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When an H level signal is input to an SSi input pin, the STxDi and SRxDi pins both become high
impedance, hence clock input is ignored. When an "L" level signal is input to an SSi input pin, clock
input becomes effective and serial communications are enabled. (i = 3 or 4)
< Master Mode (TxDi and RxDi are selected, DINC = 0) >
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The SSi input pins are used with a multiple master system. When an SSi input pin is H level, transmis-
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sion has priority and serial communications are enabled. When an L signal is input to an SSi input pin,
another master exists, and the TxDi, RxDi and CLKi pins all become high impedance. Moreover, the
trouble error interrupt request bit becomes “1”. Communications do not stop even when a trouble error
is generated during communications. To stop communications, set bits 0, 1 and 2 of the UARTi trans-
mission-reception mode register (address 032816 and 02F816 [i = 3 or 4]) to “0”.
The trouble error interrupt is used by both the bus collision interrupt and start/stop condition detection
interrupts, but the trouble error interrupt itself can be selected by setting bit 0 of UARTi special mode
register 3 (address 032516 and 02F516 [i = 3 or 4]) to “1”.
When the trouble error flag is set to “0”, output is restored to the clock output and data output pins. In
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the master mode, if an SSi input pin is H level, “0” can be written for the trouble error flag. When an SSi
input pin is L level, “0” cannot be written for the trouble error flag. In the slave mode, the “0” can be
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written for the trouble error flag regardless of the input to the SSi input pins.
Rev.1.00 Aug. 02, 2005 ^{Page 162} of 329
REJ09B0187-0100