M16C80 Datasheet, PDF (250/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
Memory expansion Mode and Microprocessor Mode (with 2 wait)
Read Timing
Vcc=5V
BCLK
ALE
CSi
ADi
BHE
RD
DB
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max*1
tcyc
td(BCLK-AD)
18ns.max*1
th(BCLK-CS)
-3ns.min
th(RD-CS)
0ns.min
th(BCLK-AD)
-3ns.min
td(BCLK-RD)
10ns.max
th(RD-AD)
0ns.min
tac2(RD-DB)*2
tac2(AD-DB)*2
th(BCLK-RD)
-5ns.min
Hi-Z
tsu(DB-BCLK)
th(RD-DB)
26ns.min*1
0ns.min
*1:It is a guarantee value with being alone. 35ns.max garantees as td(BCLK-AD)+tsu(DB-BCLK).
*2:It depends on operation frequency.
tac2(RD-DB)=(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.)
tac2(AD-DB)=(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.)
Write Timing
BCLK
ALE
CSi
ADi
BHE
WR,WRL,
WRH
18ns.max
td(BCLK-ALE)
th(BCLK-ALE)
-2ns.min
td(BCLK-CS)
18ns.max
tcyc
td(BCLK-AD)
18ns.max
td(BCLK-WR)
18ns.max
DBi
tw(WR)*3
td(DB-WR)*3
th(BCLK-CS)
-3ns.min
th(WR-CS)*3
th(BCLK-AD)
-3ns.min
th(WR-AD)*3
th(BCLK-WR)
-3ns.min
th(WR-DB)*3
*3:It depends on operation frequency.
Measuring conditions
td(DB-WR)=(tcyc x n-20)ns.min
• VCC=5V±10%
(n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.)
• Input timing voltage
th(WR-DB)=(tcyc/2-10)ns.min
:Determined with VIH=2.5V, VIL=0.8V
th(WR-AD)=(tcyc/2-10)ns.min
• Output timing voltage
th(WR-CS)=(tcyc/2-10)ns.min
:Determined with VOH=2.0V, VOL=0.8V
tw(WR)=(tcyc/2 x n-15)ns.min
(n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.)
Figure 28.4 VCC=5V timing diagram (3)
Rev.1.00 Aug. 02, 2005 ^{Page 239} of 329
REJ09B0187-0100