M16C80 Datasheet, PDF (265/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
VCC = 3V
Switching characteristics (referenced to VCC = 3V, VSS = 0V at Topr = 25^oC unless otherwise
specified)
Table 28.37 Memory expansion and microprocessor modes (with no wait)
Symbol
Parameter
Standard
Measuring condition _{Min. Max. Unit}
td(BCLK-AD) Address output delay time
25
ns
th(BCLK-AD) Address output hold time (BCLK standard)
0
ns
th(RD-AD) Address output hold time (RD standard)
0
ns
th(WR-AD) Address output hold time (WR standard)
(Note 1)
ns
td(BCLK-CS) Chip select output delay time
25
ns
th(BCLK-CS) Chip select output hold time (BCLK standard)
0
ns
th(RD-CS)
th(WR-CS)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
0
Figure 28.1 _{(Note 1)}
ns
ns
td(BCLK-ALE) ALE signal output delay time
25
ns
th(BCLK-ALE) ALE signal output hold time
–2
ns
td(BCLK-RD) RD signal output delay time
10
ns
th(BCLK-RD) RD signal output hold time
–3
ns
td(BCLK-WR) WR signal output delay time
25
ns
th(BCLK-WR)
td(DB-WR)
th(WR-DB)
WR signal output hold time
Data output delay time (WR standard)
Data output hold time (WR standard)
0
ns
(Note 1)
ns
(Note 1)
ns
tw(WR)
WR signal width
(Note 1)
ns
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) =
th(WR – DB) =
th(WR – AD) =
th(WR – CS) =
10 ⁹
f(BCLK) ^{– 40 [ns]}
10 ⁹
– 20
f(BCLK) X 2
[ns]
10 ⁹
– 20
f(BCLK) X 2
[ns]
10 ⁹
– 20
f(BCLK) X 2
[ns]
tw(WR) =
10 ⁹
– 20
f(BCLK) X 2
[ns]
Rev.1.00 Aug. 02, 2005 ^{Page 254} of 329
REJ09B0187-0100