M16C80 Datasheet, PDF (244/358 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/80 SERIES

M16C/80 Group
28. Electrical characteristics
VCC = 5V
Switching characteristics (referenced to VCC = 5V, VSS = 0V at Topr = 25^oC unless otherwise
specified)
Table 28.20 Memory expansion mode and microprocessor mode
(with wait, accessing external memory)
Symbol
Parameter
Measuring condition
Standard
Min. Max.
Unit
td(BCLK-AD) Address output delay time
18
ns
th(BCLK-AD) Address output hold time (BCLK standard)
th(RD-AD) Address output hold time (RD standard)
–3
ns
0
ns
th(WR-AD) Address output hold time (WR standard)
td(BCLK-CS) Chip select output delay time
(Note 1)
ns
18
ns
th(BCLK-CS) Chip select output hold time (BCLK standard)
–3
ns
th(RD-CS)
th(WR-CS)
td(BCLK-ALE)
th(BCLK-ALE)
Chip select output hold time (RD standard)
Chip select output hold time (WR standard)
ALE signal output delay time
ALE signal output hold time
0
ns
(Note 1)
ns
Figure 28.1
18
ns
–2
ns
td(BCLK-RD) RD signal output delay time
10
ns
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(DB-WR)
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (WR standard)
–5
ns
18
ns
–3
ns
(Note 1)
ns
th(WR-DB)
tw(WR)
Data output hold time (WR standard)
WR signal width
(Note 1)
ns
(Note 1)
ns
Note 1: Calculated according to the BCLK frequency as follows:
td(DB – WR) = ^{10 9 X n} – 20
f(BCLK)
[ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively)
th(WR – DB) =
10 ⁹
– 10
f(BCLK) X 2
[ns]
th(WR – AD) =
10 ⁹
– 10
f(BCLK) X 2
[ns]
th(WR – CS) =
10 ⁹
– 10
f(BCLK) X 2
[ns]
tw( WR) = ^{10 9 X n} – 15
f(BCLK) X 2
[ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively)
Rev.1.00 Aug. 02, 2005 ^{Page 233} of 329
REJ09B0187-0100